(S100BUS.TXT) S100 BUS PINS 8/10/83 The following is intended to be a handy reference to describe S100 IEEE-696 bus. When working with older machines, it is handy to consider them in reference to the new IEEE specification as most new peripheral boards will be made to that specification. Pin Funct Pin Funct 1 +8 volt 51 +8 volt 2 +16 volt 52 -16 volt 3 xrdy 53 gnd 4 vi0 * 54 slave clear * 5 vi1 * 55 dma 0 * 6 vi2 * 56 dma 1 * 7 vi3 * 57 dma 2 * 8 vi4 * 58 sXTRQ * 9 vi5 * 59 A19 10 vi6 * 60 SIXTN * 11 vi7 * 61 A20 12 NMI * 62 A21 13 PWRFAIL * 63 A22 14 DMA3 * 64 A23 15 A18 65 NDEF (not to be defined) 16 A16 66 NDEF ( " " " ) 17 A17 67 PHANTOM * 18 SDSB * 68 MWRT 19 CDSB * 69 RFU (reserved for future) 20 GND (old UNPROT) 70 GND (old PROT) 21 NDEF 71 RFU 22 ADSB * 72 RDY 23 DODSB* 73 INT * 24 system clock 74 HOLD * 25 pSTVAL * 75 RESET * 26 pHLDA 76 pSYNC 27 RFU 77 pWR * 28 RFU 78 pDBIN 29 A5 79 A0 30 A4 80 A1 31 A3 81 A2 32 A15 82 A6 33 A12 83 A7 34 A9 84 A8 35 DO1 85 A13 36 DO0 86 A14 37 A10 87 A11 38 DO4 88 DO2 39 DO5 89 DO3 40 DO6 90 DO7 41 DI2 91 DI4 42 DI3 92 DI5 43 DI7 93 DI6 44 sM1 94 DI1 45 sOUT 95 DI0 46 sINP 96 sINTA 47 sMEMR 97 sWO * 48 sHLTA 98 ERROR * 49 CLOCK (2 mhz) 99 POC * 50 GND 100 GND II. S100 BUS SIGNAL GROUPS 1. Data bus 16 signal lines 2. Address bus 24 signal lines 3. Status bus 8 signal lines 4. Control output bus 5 signal lines 5. Control input bus 6 signal lines 6. DMA control bus 8 signal lines 7. Vectored interrupt bus 8 signal lines 8. Utility bus 20 signal lines 1. Data bus 16 signal lines DO0-7 Data out from master gated by DODSB. The data bus is implimented with tri state bus drivers which can be turned off when DMA mode is implimented from another master such as a disk controller. Note that the two busses can be ganged for use in sixteen bit operations by asserting SIXTN. DI0-7 Data bus into master. 2. Address bus 24 signal lines A0-15 Address bus for normal 64k memory access. This bus is gated by ADSB for DMA operations. A16-23 Extended address bus for 24 bit addressed systems. Note that this system is at odds with the bank select system now used by CPM-3 and MPM. It is very probable that more systems in the future will go to this style of memory management as it effectivly does away with the '48k bank' scheme. One system which bears watching is Zilog's new Z800. This system has extended management built into it. 3. Status bus 8 signal lines sMEMR Memory read This signal is used for memory read operations. It is derived from Z80 Mreq and Rd signals. When used in memory, it is qualified by Bsel (on board bank select), Pdbin and Phantom*. It is gated at the master by SDSB for DMA operations. sM1 Op-code fetch Machine cycle M1 is used for Instruction fetch. It is not used by memory or I/O operations. This signal is gated at the master by SDSB for DMA operations. sINP input I/O input to master, status and strobe signal.This signal is gated at the master by SDSB for DMA operations. sOUT output I/O output from master, status and strobe signal.This signal is gated at the master by SDSB for DMA operations. sWO* Write cycle Write cycle write status and strobe. This signal needs qualification as it is effective for both I/O and memory operations. Usually it is used with sOUT. This signal is gated at the master by SDSB for DMA operations. Older systems often used MWRTE to strobe data to memory. The 696 specification discourages this as it is not a gated signal and will cause contention in DMA systems. sINTA Interrupt acknowledge This status line is driven by the master in response to an interrupt request. It should be used by the interrupting device to strobe data into the DI0-7 bus. sHLTA Halt acknowledge This status line is set by the master when it enters into a Halt state as a result of excuting a Halt instruction. This situation occurs when a subsystem is resting in a halt state while waiting for an interrupt to bring it active again. An example of this is a disk controller. sXTRQ* Sixteen bit data request This status line is asserted by the master to request a sixteen bit transfer. 4. Control output bus 5 signal lines pSYNC Processor synchronize This signal becomes active at the beginning of a machine cycle and stays active for one system clock period. pSTVAL* Processor status valid This signal anded with pSYNC is used to indicate that valid information is available on address and status buses. pDBIN Processor Data bus in This status line is used to qualify data during a memory or I/O read. pWR* Processor Write This status line is used to qualify data during a memory or I/O write. pHLDA Processor Hold acknowledge This status line indicates that the master has released the bus to another master. 5. Control input bus 6 signal lines RDY Slave ready This signal is used by a slave to induce the master to generate a wait state. XRDY Slave ready (alternate) This signal is used by a slave to induce the master to generate a wait state. It has the same function as RDY INT* Slave interrupt request This signal is asserted by a slave to initiate an interrupt cycle. This should be maintained as a level for the duration of the interrupt cycle. NMI* Non maskable interrupt This signal is a non maskable interrupt and as such is used for the highest priority event. This line does not have to be maintained as a level. HOLD* Hold request This signal is asserted by the temporary master to induce the master to relinquish the bus. This line should be maintained as a level until the temporary master is done with the bus. An example of this is a DMA transfer. SIXTN* Sixteen Acknowledge 6. DMA control bus 8 signal lines DMA0-3 DMA priority interrupt lines These lines constitute an encodable priority interrupt system. Using four lines permits up to 16 sub-masters to contend for the bus. ADSB* Address Disable When DMA is granted by the permanent master, the ADSB line is asserted by the temporary master. This lines tri-states the address signals at the master. DODSB* Data out disable This signal asserted by the temporary master during a DMA operation tri-states the DO0-7 lines at the master. SDSB* Status bus disable This signal asserted by the temporary master during a DMA operation tri-states the Status lines at the master. CDSB* Control output disable This signal asserted by the temporary master during a DMA operation tri-states the Control lines at the master. 7. Vectored interrupt bus 8 signal lines VI0-7 These signals form a vectored prority interrupt system to the master. They are often connected through a priority handler such as Mosteks MK3882 CTC circuit. 8. Utility bus 20 signal lines +8 VOLT (2 lines) +16 VOLT -16 VOLT GROUND (5 lines) SYSTEM CLOCK System clock (4mhz or higher) This line is the system clock. It is used to control all bus cycles and timing. CLOCK 2 mhz clock This clock is an independent clock which may be used as a time base to set up baud rate generators. RESET* Pushbutton reset SLAVE CLR* slave reset This line is used to reset all slaves. POC* power on clear MWRT* Memory write This line has been used on older systems to strobe memory write operations. It is not gated by DMA CDSB control disconnect, and is therefore unusable in DMA operations. The current accepted scheme is to use sWO for memory write control. PHANTOM* phantom memory control This line is used to remove memory from the system during the time that temporary memory is active. Most commonly this permits the boot prom to be pulled into active service only when it is addressed. ERROR* slave error NDEF (3 lines) These lines are not to be defined and are reserved for various manufacturers use. PWRFAIL* RFU (5 lines) These lines are reserved for future use. Contributed by: Pete Mack Simi Valley, Ca.