Hewlett-Packard 2116B, 2115A, and 2114A Instruction Set
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Abbreviations:

        m      Memory location.
        I      Indirect address indicator.
        C      Clear flag indicator.
        A      A Register.
        B      B Register.
        E      E Register.
        sc     Channel Select code.
        lit    Literal value.
        b      Bit number.


Memory Reference
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Jump and Increment-Skip

ISZ   m [,I]     Increment, then skip if zero.
JMP   m [,I]     Jump to m.
JSB   m [,I]     Jump to subroutine at m.

Add, load, and store

ADA   m [,I]     Add to A.
ADA   lit        Add literal to A.
ADB   m [,I]     Add to B.
ADB   lit        Add literal to B.
LDA   m [,I]     Load into A.
LDA   lit        Load literal into A.
LDB   m [,I]     Load into B.
LDB   lit        Load literal into B.
STA   m [,I]     Store A.
STB   m [,I]     Store B.

Logical

AND   m [,I]     AND to A.
AND   lit        AND literal to A.
XOR   m [,I]     Exclusive OR to A.
XOR   lit        Exclusive OR literal to A.
IOR   m [,I]     Inclusive OR to A.
IOR   lit        Inclusive OR literal to A.
CPA   m [,I]     Compare to A, skip if unequal.
CPA   lit        Compare literal to A, skip if unequal.
CPB   m [,I]     Compare to B, skip if unequal.
CPB   lit        Compare literal to B, skip if unequal.

Register Reference
-------- ---------

Shift-Rotate

CLE              Clear E.
ALS              Shift A left one bit.
BLS              Shift B left one bit.
ARS              Shift A right one bit.
BRS              Shift B right one bit.
RAL              Rotate A left one bit.
RBL              Rotate B left one bit.
RAR              Rotate A right one bit.
RBR              Rotate B right one bit.
ALR              Shift A left one bit, clear sign.
BLR              Shift B left one bit, clear sign.
ERA              Rotate E and A right one bit.
ERB              Rotate E and B right one bit.
ELA              Rotate E and A left one bit.
ELB              Rotate E and B left one bit.
ALF              Rotate A left four bits.
BLF              Rotate B left four bits.
SLA              Skip if LSB of A is clear.
SLB              Skip if LSB of B is clear.

No operation

NOP              No operation.

Alter-Skip

CLA              Clear A.
CLB              Clear B.
CMA              Complement A.
CMB              Complement B.
CCA              Clear and complement A (=1s).
CCB              Clear and complement B (=1s).
CLE              Clear E.
CME              Complement E.
CCE              Clear and complement E (=1).
SEZ              Skip if E=zero.
SSA              Skip if sign A is zero.
SSB              Skip if sign B is zero.
INA              Increment A by one.
INB              Increment B by one.
SZA              Skip if A is zero.
SZB              Skip if B is zero.
SLA              Skip if LSB of A is zero.
SLB              Skip if LSB of B is zero.
RSS              Reverse Sense of Skip (skip in nonzero).

Input/Output, Overflow, and Halt
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Input/Output

STC   sc [,C]    Set I/O Control bit.
CLC   sc [,C]    Clear I/O Control bit. If sc=0, clear all bits.
LIA   sc [,C]    Load into A from I/O Channel.
LIB   sc [,C]    Load into B from I/O Channel.
MIA   sc [,C]    Merge (or) into A from I/O Channel.
MIB   sc [,C]    Merge (or) into B from I/O Channel.
OTA   sc [,C]    Output from A into I/O Channel.
OTB   sc [,C]    Output from B into I/O Channel.
STF   sc         Set I/O flag.
CLF   sc         Clear I/O flag.
SFC   sc         Skip if I/O flag is clear (=0).
SFS   sc         Skip if I/O flag is set (=1).

Overflow

CLO              Clear overflow bit (=0).
STO              Set overflow bit (=1).
SOC   [C]        Skip if overflow clear (=0).
SOS   [C]        Skip if overflow set (=1).

Halt

HLT   [sc [,C]]  Halt computer.

Extended Arithmetic Unit
-------- ---------- ----

MPY   m [,I]     Multiply.
MPY   lit        Multiply.
DIV   m [,I]     Divide.
DIV   lit        Divide.
DLD   m [,I]     Double load.
DLD   lit        Double load.
DST   m [,I]     Double store.
DST   lit        Double store.
ASR   b          Arithmetically shift BA right b bits.
ALS   b          Arithmetic long shift left.
RRR   b          Rotate BA right b bits.
RRL   b          Rotate BA left b bits.
LSR   b          Logically shift BA right b bits.
LSL   b          Logically shift BA left b bits.
SWP              Swap A and B.